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? 2008 fairchild semiconductor corporation www.fairchildsemi.com application note AN-6076 design and application guide of bootstrap circuit for high-voltage gate-drive ic rev. 1.0.0 ? 9/30/08 www.fairchildsemi.com 1. introduction the purpose of this paper is to demonstrate a systematic approach to design high-performance bootstrap gate drive circuits for high-frequency, high-power, and high-efficiency switching applications using a power mosfet and igbt. it should be of interest to pow er electronics engineers at all levels of experience. in the most of switching applications, efficiency focuses on switching losses that are mainly depen- dent on switching speed. therefore, the switching character- istics are very important in most of the high-power switching applications presented in this paper. one of the most widely used methods to supply power to the high-side gate drive cir- cuitry of the high-voltage gate-drive ic is the bootstrap power supply. this bootstrap power supply technique has the advantage of being simple and low cost. however, it has some limitations, on time of duty-cycle is limited by the requirement to refresh the charge in the bootstrap capacitor and serious problems occur when the negative voltage is pre- sented at the source of the switching device. the most popu- lar bootstrap circuit solutions are analyzed; including the effects of parasitic elements, the bootstrap resistor, and capacitor; on the charge of the floating supply application. 2. high-speed gate-driver circuitry 2.1 bootstrap gate-drive technique the focus of this topic is the bootstrap gate-drive circuit requirements of the power mosfet and igbt in various switching-mode power-conversion applications. where input voltage levels prohibit the use of direct-gate drive cir- cuits for high-side n-channel power mosfet or igbt, the principle of bootstrap gate-drive technique can be consid- ered. this method is utilized as a gate drive and accompany- ing bias circuit, both referenced to the source of the main switching device. both the driver and bias circuit swing between the two input voltage rails together with the source of the device. however, the driver and its floating bias can be implemented by low-voltage circuit elements since the input voltage is never applied across their components. the driver and the ground referenced control signal are linked by a level shift circuit that must tolerate the high-voltage differ- ence and considerable capaciti ve switching currents between the floating high-side and ground-referenced low-side cir- cuits. the high-voltage gate-drive ics are differentiated by unique level-shift design. to maintain high efficiency and manageable power dissipation, the level-shifters should not draw any current during the on-time of the main switch. a widely used technique for these applications is called pulsed latch level translators, shown in figure 1. figure 1. level-shifter in high-side drive ic 2.2 bootstrap drive circuit operation the bootstrap circuit is useful in a high-voltage gate driver and operates as follows. when the v s goes below the ic supply voltage v dd or is pulled down to ground (the low- side switch is turned on and the high-side switch is turned off), the bootstrap capacitor, c boot , charges through the bootstrap resistor, r boot , and bootstrap diode, d boot , from the v dd power supply, as shown in figure 2. this is pro- vided by v bs when v s is pulled to a higher voltage by the high-side switch, the v bs supply floats and the bootstrap diode reverses bias and blocks the rail voltage (the low-side switch is turned off and high-side switch is turned on) from the ic supply voltage, v dd . figure 2. bootstrap power supply circuit uvlo pulse generator r r s q v b noise canceller shoot-through current compensated gate driver ho v s in com dc supply load v dd q1 q2 rg2 rg1 d boot c boot i load r boot v dd lo ho v b v s bootstrap charge current path bootstrap discharge current path
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 2 2.3 drawback of bootstrap circuitry the bootstrap circuit has the advantage of being simple and low cost, but has some limitations. duty-cycle and on time is limited by the requirement to refresh the charge in the bootstrap capacitor, c boot . the biggest difficulty with this circuit is that the negative voltage present at the source of the switching device during turn-off causes load current to suddenly flow in the low-side freewheeling diode, as shown in figure 3. this negative voltage can be trouble for the gate driver?s out- put stage because it directly affects the source v s pin of the driver or pwm control ic and might pull some of the inter- nal circuitry significantly below ground, as shown in figure 4. the other problem caused by the negative voltage tran- sient is the possibility to develop an over-voltage condition across the bootstrap capacitor. the bootstrap capacitor, c boot , is peak charged by the boot- strap diode, d boot , from v dd the power source. since the v dd power source is referenced to ground, the maximum voltage that can build on the bootstrap capacitor is the sum of v dd and the amplitude of the negative voltage at the source terminal. figure 3. half-bridge application circuits figure 4. v s waveforms during turn-off 2.4 cause of negative voltage on v s pin a well-known event that triggers v s go below com (ground) is the forward biasing of the low-side freewheeling diode, as shown in figure 5. major issues may appear during commutation, just before the freewheeling diode starts clamping. in this case, the inductive parasitic elements, ls1 and ls2, may push v s below com, more than as described above or normal steady-state condition. the amplitude of negative voltage is proportional to the par- asitic inductances and the turn-off speed, di/dt, of the switch- ing device; as determined by the gate drive resistor, r gate , and input capacitance, c iss , of switching device. it is sum of c gs and c gd , called miller capacitance. figure 5. step-down converter applications figure 6 shows the waveforms of the high-side, n-channel mosfet during turn-off. figure 6. waveforms during turn-off lo com ho vs dc supply i free vdd vb q1 q2 rg2 rg1 ls1 ls2 high side off freewheeling path hin lin hin lin i load c boot d boot r boot c in -v s t hin freewheeling t v s -com q1 v b in gnd ho v s v dd input d1 hvic v cc v dc d boot c boot r gate c drv c out l s1 l s2 c c i load i free a b gnd - v s v out v dc +v gs,miller v dc v bs recovery time a-point b-point c-point v gs =b-c point
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 3 2.5 effects in the undershoot spike on v s pin if undershoot exceeds the absolute maximum rating speci- fied in the datasheet, the gate drive ic suffers damage or the gate drive ic temporarily latches in its current state. figure 7 shows the high-side output not changed by input signal, which represents latch-up condition where external, main, high- and low-side switches are in short-circuit condi- tion in half-bridge topology. figure 7. waveforms in case of latch-up if undershoot exceeds the absolute maximum rating speci- fied in the datasheet, the gate drive ic does not suffer dam- age. however, the high-side output does not respond to input transitions while in undershoot condition as shown in figure 8. in this situation, the level shifter of the high-side gate driver suffers from a lack of the operating voltage headroom. this should be noted, but proves trivial in most applications, as the high-side is not usually required to change state imme- diately following a switching event. figure 8. waveforms in case of signal missing 2.6 consideration of latch-up problem the most integrated high-voltage gate-drive ics have para- sitic diodes, which, in forward or reverse break-down, may cause parasitic scr latch-up. the ultimate outcome of latch- up often defies prediction and can range from temporary erratic operation to total device failure. the gate-drive ic may also be damaged indirectly by a chain of events follow- ing initial overstress. for example, latch-up could conceiv- ably result in both output drivers assuming a high state, causing cross-conduction followed by switch failure and, finally, catastrophic damage to the gate-drive ic. this failure mode should be considered a possible root-cause, if power transistors and/or gate-drive ic are destroyed in the applica- tion. the following theoretical extremes can be used to help explain the relationships between excessive v s undershoot and the resulting latch-up mechanism. in the first case, an "ideal bootstrap circuit" is used in which v dd is driven from a zero-ohm supply with an ideal diode feed v b , as shown in figure 9. when the high current flow- ing through freewheeling diode, v s voltage is below ground level by high di/dt. this time, latch-up risk appears since internal parasitic diode, d bs of the gate driver ultimately enters conduction from v s to v b , causing the undershoot voltage to sum with v dd , causing the bootstrap capacitor to overcharge, as shown figure 10. for example , if v dd =15v, then v s undershoot in excess of 10v forces the floating supp ly above 25v, risking break- down in diode d bs and subsequent latch-up. figure 9. case 1: ideal bootstrap circuits figure 10. v b and v s waveforms of case 1 input output latch-up problem input output signal missing problem com v b v s gate driver v dd d bs v s gnd v b high v bs
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 4 suppose that the bootstrap supply is replaced with the ideal floating supply, as shown in figure 11, such that v bs is fixed under all circumstances. note that using a low impedance auxiliary supply in place of a bootstrap circuit can approach this situation. this time, latch-up risk appears if v s under- shoot exceeds the v bs maximum specified in datasheet, since parasitic diode d bcom ultimately enters conduction from com to v b , as shown in figure 12. figure 11. case 2: ideal floating supply figure 12. v b and v s waveforms of case 2 a practical circuit is likely to fall somewhere between these two extremes, resulting in both a small increase of v bs and some v b droop below v dd , as shown in figure 13. figure 13. typical response of v b and v s exactly which of the two extremes is prevalent can be checked as follows. if the v s pins undershoot spike has a time length that is on order of tenths of nanoseconds; the bootstrap capacitor, c boot , can become overcharged and the high-side gate-driver circuit has damage by over-voltage stress because it exceeds an absolute maximum voltage (v bsmax ) specified in datasheet. design to a bootstrap cir- cuit, that does not exceed the absolute maximum rating of high-side gate driver. 2.7 effect of parasitic inductances the amplitude of negative voltage is: to reduce the slope of current flowing in the parasitic induc- tances to minimize the derivative terms in equation 1. for example , if a 10 ampere, 25v gate driver with 100nh parasitic inductance switches in 50ns, the negative voltage spike between v s and ground is 20v. 3. design procedure of bootstrap components 3.1 select the bootstrap capacitor the bootstrap capacitor (c boot ) is charged every time the low-side driver is on and the output pin is below the supply voltage (v dd ) of the gate driver. the bootstrap capacitor is discharged only when the high-side switch is turned on. this bootstrap capacitor is the supply voltage (v bs ) for the high circuit section. the first parameter to take into account is the maximum voltage drop that we have to guarantee when the high-side switch is in on state. the maximum allowable volt- age drop (v boot ) depends on the minimum gate drive volt- age (for the high-side switch) to maintain. if v gsmin is the minimum gate-source voltage, the capacitor drop must be: where: v dd = supply voltage of gate driver [v]; and v f = bootstrap diode forward voltage drop [v] the value of bootstrap capacitor is calculated by: where q total is the total amount of the charge supplied by the capacitor. the total charge supplied by th e bootstrap capacitor is calcu- lated by equation 4.: (4) where: q gate = total gate charge; i lkgs = switch gate-source leakage current; i lkcap = bootstrap capacitor leakage current; i qbs = bootstrap circuit quiescent current; i lk = bootstrap circuit leakage current; q ls = charge required by the internal level shifter, which is set to 3nc for all hv gate drivers; com v b v s gate driver v cc d bcom v cc v s gnd v b v b below com v s gnd v b v b close to com increased v bs (1) dt di s s fdboot rboot l l v v com ) ( ) ( v 2 1 s + ? + ? = ? gsmin f dd boot v v v v ? ? = (2) boot total boot v q c = (3) ls on lkdiode lk qbs lkgs lkcap gate total q t i i i i i q q + ? + + + + + = ) (
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 5 t on = high-side switch on time; and i lkdioded = bootstrap diode leakage current. the capacitor leakage current is important only if an electro- lytic capacitor is used; otherwise, this can be neglected. 3.2 select the bootstrap resistor when the external bootstrap resistor is used, the resistance, r boot , introduces an additional voltage drop: where: i charge = bootstrap capacitor charging current; r boot = bootstrap resistance; and t charge = bootstrap capacitor charging time (the low-side turn-on time). do not exceed the ohms (typically 5~10 ) that increase the v bs time constant. this voltage drop of bootstrap diode must be taken into account when the maximum allowable voltage drop (v boot ) is calculated. if this drop is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. for example: evaluate the bootstrap capacitor value when the external bootstrap diode used. gate drive ic = fan7382 (fairchild) switching device = fcp20n60 (fairchild) bootstrap diode = uf4007 v dd = 15v q gate = 98nc (maximum) i lkgs = 100na (maximum) i lkcap = 0 (ceramic capacitor) i qbs = 120a (maximum) i lk = 50a (maximum) q ls = 3nc t on = 25s (duty=50% at f s =20khz) i lkdiode = 10na if the maximum allowable voltage drop on the bootstrap capacitor is 1.0v during the high side switch on state, the minimum capacitor value is calculated by equation 3. the value of bootstrap capacitor is calculated as follows: the voltage drop due to the external diode is nearly 0.7v. assume the capacitor charging time is equal to the high-side on-time (duty cycle 50%). according to different bootstrap capacitor values, the following equation applies: suggested values are within the range of 100nf ~ 570nf, but the right value must be selected according to the application in which the device is used. wh en the capacitor value is too large, the bootstrap charging time slows and the low-side on time might be not long enough to reach the bootstrap voltage. 4. consideration of bootstrap application circuits 4.1 bootstrap startup circuit the bootstrap circuit is useful in high-voltage gate driver, as shown in figure 1. however, it has a initial startup and lim- ited charging a bootstrap capacitor problem when the source of the main mosfet (q1) and the negative bias node of bootstrap capacitor (c boot ) are sitting at the output voltage. bootstrap diode (d boot ) might be reverse biased at startup and main mosfet (q1) has a insufficient turn-off time for the bootstrap capacitor to maintain a required charge, as shown in figure 1. in certain applications, like in battery chargers, the output voltage might be present before input power is applied to the converter. delivering the initial charge to the bootstrap capacitor (c boot ) might not be possible, depending on the potential difference between the supply voltage (v dd ) and output voltage (v out ) levels. assuming there is enough voltage differential between input voltage (v dc ) and output voltage (v out ), a circuit comprised of startup resistor (r start ), startup diode (d start ), and zener diode (d z ) can solve the problem, as shown in figure 14. in this startup cir- cuit, startup diode d start serves as a second bootstrap diode used for charging the bootstrap capacitor (c boot ) at power up. bootstrap capacitor (c boot ) is charged to the zener diode of d z , which is supposed to be higher than the driver's supply voltage (v dd ) during normal operation. the charge current of the bootstrap capacitor and the zener cur- rent are limited by the startup resistor. for best efficiency, the value of startup resistor should be selected to limit the current to a low value, since the bootstrap path through the startup diode is permanently in the circuit. charge boot charge rboot t r i v ? = (5) ] [ 10 2 . 105 ) 10 3 ( )} 10 25 ( ) 10 10 10 50 10 120 10 100 {( ) 10 98 ( 9 9 6 9 6 6 9 9 c q total ? ? ? ? ? ? ? ? = + + + + + = (6) ] [ 105 1 10 2 . 105 9 nf v q c boot total boot ? = = ? (7) (8) v boot q total c boot -------------------- - = 100nf v boot ? 1.05 v = 150nf v boot ? 0.7 v = 220nf v boot ? 0.48 v = 570nf v boot ? 0.18 v =
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 6 figure 14. simple bootstrap startup circuit 4.2 resistor in series with bootstrap diode in the first option, the bootstrap circuit includes a small resistor, r boot , in series with bootstrap diode, as shown in figure 15. the bootstrap resistor, r boot , provides current limit only during a bootstrap charging period which repre- sents when the v s goes below the ic supply voltage, v dd , or is pulled down to ground (the low-side switch is turned on and the high-side switch is turned off). the bootstrap capaci- tor, c boot , charge through the bootstrap resistor, r boot , and diode, d boot , from the v dd power supply. the boot- strap diode must have a break-down voltage (bv) larger than v dc and a fast recovery time to minimize the amount charge fed back from the bootstrap capacitor to v cc power supply. figure 15. adding a series resistor with d boot this method has the advantage of being simple for limiting the current when the bootstrap capacitor is initially charged, but it has some limitations. duty-cycle is limited by the requirement to refresh the charge in the bootstrap capacitor, c boot , and there are startup problems. do not exceed the ohms (typically 5~10 ) that would increase the v bs time constant. the minimum on-time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time constant. the time constant depends on the values of bootstrap resistance, capacitance, and duty cycle of switching device calculated in following equation: where r boot is the bootstrap resistor; c boot is the boot- strap capacitor; and d is the duty cycle. for example, if r boot =10, c boot =1f, and d=10%; the time constant is calculated in following equation: even with a reasonably large bootstrap capacitor and resis- tor, the time constant may be large. this method can mitigate the problem. unfortunately, the series resistor does not pro- vide a foolproof solution against an over voltage and it slows down the recharge process of the bootstrap capacitor. 4.3 resistor between v s and v out in the second option, the bootstrap circuit includes a small resistor, r vs , between v s and v out , as shown in figure 16. suggested values for r vs are in the range of some ohms. figure 16. adding r vs in bootstrap circuit the r vs works as, not only bootstrap resistor, but also turn- on and turn-off resistors, as shown in figure 17. the boot- strap resistor, turn-on, and turn -off resistors are calculated by the following equations: figure 17. current paths of turn-on and turn-off input r boot d boot c boot c out d l q1 v out v dc v dd d start r start d z r gate com hin v s v b ho v dd r boot q1 v b in gnd ho v s v cc l1 in d1 hvic v cc v dc d boot c boot r gate c drv c out v out (9) r boot c boot ? d ---------------------------------------- s [] = (10) r boot c boot ? d ---------------------------------------- 10 1 6 ? ? 0.1 ------------------ 1 0 0 s [] === q1 v b in gnd ho v s v cc l1 in d1 hvic v cc v dc d boot c boot r gate c drv c out r boot r vs v out r boot ? r boot r vs + = (11) r on ? r gate r vs + = (12) r off ? r gate r vs + = (13) q1 v b in gnd ho v s v cc l1 in d1 v cc d boot c boot r gate c drv c out r boot r vs v out i bchg i turn-on i turn-off
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 7 4.4 clamping diode for v s and relocation gate resistor in the third option, the bootstrap relocates a gate resistor between v s and v out and adds a low forward-voltage drop schottky diode from ground to v s , as shown in figure 18. the difference between v b and v s should be kept inside the absolute maximum specificati on in the datasheet and must be satisfied by the following equation: figure 18. clamping structure 4.5 relocated gate resistor; double purpose the gate resistor sets the turn-on and turn-off speeds in the mosfet and provides current limiting for the schottky diode during the negative voltage transient of the source ter- minal of the main switch. in additional, the bootstrap capaci- tor is protected against over voltage by the two diodes connected to the ends of c boot . the only potential hazard by this circuit is that the charging current of the bootstrap capacitor must go through gate resistor. the time constant of c boot and r gate slows the recharge process, which might be a limiting factor as the pwm duty cycle. the fourth options includes relocating a gate resistor between v s and v out and a clamp device should be posi- tioned between ground and v s , as shown in figure 19, where a zener diode and a 600v diode are placed. the zener volt- age must be sized accordin g to the following rule: figure 19. clamping structure with zener diode 5. choose current capability hvic the approximate maximum gate charge q g that can be switched in the indicated time for each driver current rating is calculated in table 1: table 1. example hvic current-drive capability note: 1. for a single 4a, parallel the two channels of a dual 2a! for example , a switching time of 100ns is: 1% of the converter switching period at 100khz; 3% of the converter switching period at 300khz; etc. 1. needed gate driver current ratings depend on what gate charge q g must be moved in switching time t sw-on/off (because average gate current during switching is i g ): 2. the maximum gate charge, q g , is read from the mosfet datasheet. if the actual gate-drive voltage v gs is different from the test condition in the specifications table, use the v gs vs. q g curve instead. multiply the datasheet value by the number of mosfets in parallel. 3. t sw_on/off is how fast the mosfet should be switched. if unknown, start with 2% of the switching period t sw : if channel (v-i) switching loss is dominated by one switch- ing transition (turn-on or turn-off), size the driver for that transition. for clamped inductive switching (the usual case), channel switching loss for each transition is estimated as: where v ds and i d are maximum values during the switching interval. 4. the approximate current drive capability of gate driver may be calculated like below (1) sourcing current capability (turn-on) max _ abs bs s b v v v < ? (14) q1 v b in gnd ho v s v cc l1 in d1 hvic v cc v dc d boot c boot r gate c drv c out d scht v out (15) v b v s ?v bs absmax , < q1 v b in gnd ho v s v dd l1 in d1 hvic v cc v dc d boot c boot r gate c drv c out v out d2 d z needed current rating switching time (t sw_on/off ) 100ns 50ns maximum gate charge (q g, m a x ) 2a 133nc 67nc 4a 267nc 133nc 9a 600nc 300nc off on sw g sw av g t q i / _ . . = (16) (17) t swon off , 0.02 t sw 0.02 f sw ----------- == (18) e sw 0.5 v ds i d t sw joules = (19) i source 1.5 q g t sw on , -------------------
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 8 (2) sinking current capability (turn-off) where: q g = mosfet gate charge at v gs = v dd ; t sw_on/off = mosfet switch turn-on / turn-off time; and 1.5 = empirically determined factor (influenced by delay through the driver input stages and parasitic elements). 6. gate resistor design procedure the switching speed of the output transistor can be con- trolled by values of turn-on and turn-off gate resistors con- trolling the turn-on and turn-off current of gate driver. this section describes basic rules for values of the gate resistors to obtain the desired switching time and speed by introduc- ing the equivalent output resistor of the gate driver. figure 20 shows the equivalent circuit of gate driver and current flow paths during the turn-on and turn-off, including a gate driver and switching devices. figure 20. gate driver equivalent circuit figure 21 shows the gate-charge transfer characteristics of switching device during turn-on and turn-off. figure 21. gate charge transfer characteristics 6.1 sizing the turn-on gate resistor turn-on gate resistor, r g(on) , can be chosen to obtain the desired switching time by using switching time, t sw . to determine a value of resistor using the switching time, sup- ply voltage, v dd (or v bs ), equivalent on resistance (r drv(on) ) of the gate driver, and switching device parame- ters (q gs , q gd , and v gs(th) ) are needed. the switching time is defined as the time spent to reach the end of the plateau voltage (a total q gd + q gd has been pro- vided to the mosfet gate), as shown in figure 21. the turn-on gate resistor calculated as follows: where r g(on) is the gate on resistance and r drv(on) is the driver equivalent on resistance. 6.2 output voltage slope turn-on gate resistor r g(on) can be determined by control output slope (dv out /dt). while the output voltage has a non- linear behavior, the maximum output slope can be approxi- mated by: inserting the expression yielding i g(avr) and rearranging: where c gd(off) is the miller effect capacitor, specified as c rss in the datasheet. 6.3 sizing the turn-off gate resistor the worst case in sizing the turn -off resistor is when the drain of the mosfet in turn-off state is forced to commu- tate by external events. in this case, dv/dt of the output node induces a parasitic cur- rent through c gd flowing in r g(off) and r drv(off) , as shown in figure 22 the following describes how to size the turn-off resistor when the output dv/dt is cau sed by the companion mosfet turning-on, as shown in figure 22. for this reason, the off-resistance must be sized according to the application worst case. the following equation relates the mosfet gate threshold voltage to the drain dv/dt: (20) i sink 1.5 q g t sw off , --------------------- - v dc driver v dd gnd driver r gate c gd c gs c gd c ds 1 1 2 vb vs lo ho turn-on turn-off on off on off v dd v bs c gs r g( on) 2 hvic v out r g( off) dv out dt dv out dt r drv(on) r drv(off ) (21) i gavr () q gs q gd + t sw ------------------------ - = (22) r total r gon () r drv on () + v dd v gs + i gavr () -------------------------- - == (23) dv out dt ----------------- - i gavr () c gd off () ------------------- = (24) r total v dd v gs th () ? c gd off () dv out dt ----------------- - ? ------------------------------------------ =
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 9 figure 22. current paths: low-side switch turned off, high-side switch turned on rearranging the equation yields: 6.4 design example determine the turn-on and off gate resistors using the fair- child mosfet with fcp20n60 and gate driver with fan7382. the power mosfet of fcp20n60 parameters are as follows: q gs =13.5nc, q gd =36nc, c gd =95pf, v gs(th) =5v, v gs(th)min =3v 6.4.1 turn-on gate resistance 1) if the desired switching time is 500ns at v dd =15v, the average gate charge current is calculated as: the turn-on resistance value is about 58 . 2) if dv out /dt=1v/ns at v dd =15v, the total gate resistor is as calculated as: the turn-on resistance value is about 62 . 6.4.2 turn-off gate resistance if dv out /dt=1v/ns, the turn-off gate resistor is calculated as: 7. power dissipation considerations 7.1 gate driver power dissipation the total power dissipation is the sum of the gate driver losses and the bootstrap diode losses. the gate driver losses are comprised of the static and dynamic losses related to the switching frequency, output load capacitance on high- and low-side drivers, and supply voltage, v dd . the static losses are due to the quiescent currents from the voltage supplies v dd and ground in low-side driver and the leakage current in the level shif ting stage in high-side driver, which are dependent on the voltage supplied on the v s pin and proportional to the duty cycle when only the high-side power device is turned on. the dynamic losses are defined as follows: in the low-side driver, the dynamic losses are due to two different sources. one is due to whenever a load capacitor is charged or dis- charged through a gate resistor, half of energy that goes into the capacitance is dissipated in the resistor. the losses in the gate drive resistance, internal and external to the gate driver, and the switching loss of the internal cmos circuitry. also, the dynamic losses of the high-side driver have two different sources. one is due to the level-shifting circuit and one due to the charging and discharg ing of the capacitance of the high side. the static losses are neglected here because the total ic power dissipation is mainly dynamic losses of gate drive ic and can be estimated as: figure 23 shows the calculated gate driver power dissipation versus frequency and load capacitance at v dd =15v. this plot can be used to approximate the power losses due to the- gate driver. v dc driver v dd gnd dri ver r gate c gd c gs c gd c ds 1 2 vb vs lo ho turn-on turn-off on off on off v dd v bs c gs r g( on) hvic r g( off) r drv(on) r drv(off ) dv out dt i load load dt dv c r r i r r v out gd drv off g g off drv off g th gs + = + ) {( } ) {( ) ( ) ( ) ( ) ( ) ( (25) ) ( ) ( g(off) r drv out gd th gs r d t dv c v ? ? (26) ] [ 99 500 5 . 13 36 ) ( ma ns nc nc t q q i sw gd gs avr g = + = + = (27) ] [ 101 99 5 15 ) ( ) ( = ? = ? = ma i v v r avr g th gs dd total (28) ] [ 43 350 15 ) ( = = ma v i v r source dd on drv (29) ] [ 105 10 10 95 5 15 9 12 ) ( ) ( = ? = ? ? = ? d t dv c v v r out off gd th gs dd total (30) ] [ 43 350 15 ) ( = = ma v i v r source dd on drv (31) ] [ 23 650 15 ) ( = = ma v i v r sink dd off drv (32) 6 . 8 23 10 10 95 3 r 9 12 ) ( min ) ( g(off) = ? = ? ? ? drv out gd th gs r d t dv c v (33) ] [ 2 2 w v f c p dd s l dgate = (34 )
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 10 figure 23. gate driver total power dissipation the bootstrap circuit power dissipation is the sum of the bootstrap diode losses and the bootstrap resistor losses if any exist. the bootstrap diode loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. since each of these events happens once per cycle, the diode power loss is proportional to switching frequency. larger capacitive loads require more current to recharge the bootstrap capacitor, resulting in more losses. higher input voltages (v dc ) to the half-bridge result in higher reverse recovery losses. the total ic power dissipa- tion can be estimated by summing the gate driver losses with the bootstrap diode losses, except bootstrap resistor losses. if the bootstrap diode is within the gate driver, add an exter- nal diode in parallel with the internal bootstrap diode because the diode losses can be significant. the external diode must be placed close to the gate driver to reduce para- sitic series inductance and significantly lower forward volt- age drop. 7.2 package thermal resistance the circuit designer must provide: ? estimate power dissipation of gate driver package ? the maximum operating junction temperature t j, max,opr , e.g., 120c for these drivers if derated to 80% of t j,max =150c. ? maximum operating lead temperature t l,max,opr , approximately equal to the maximum pcb temperature underneath the driver, e.g., 100c. ? maximum allowable junction -to-lead thermal resistance is calculated by: 8. general guidelines 8.1 printed circuit board layout the layout for minimized parasitic inductances is as follows: ? direct tracks between switches with no loops or deviation. ? avoid interconnect links. these can add significant inductance. ? reduce the effect of lead-inductance by lowering package height above the pcb. ? consider co-locating both power switches to reduce track length. ? placement and routing for decoupling capacitor and gate resistors as close as possible to gate drive ic. ? the bootstrap diode as close as possible to bootstrap capacitor. 8.2 bootstrap components the bootstrap resistor (r boot ) must be considered in sizing the bootstrap resistance and the current developed during ini- tial bootstrap charge. if the resistor is needed in series with the bootstrap diode, verify that v b does not fall below com (ground), especially during startup and extremes of fre- quency and duty cycle. the bootstrap capacitor (c boot ) uses a low-esr capacitor, such as ceramic capacito r. the capacitor from v dd to com supports both the low-side driver and bootstrap recharge. a value at least ten times higher than the bootstrap capacitor is recommended. the bootstrap diode must use a lower forward voltage drop and switching time as soon as possible for fast recovery, such as ultra-fast. 0.1 1 10 100 1000 0.01 0.1 1 power [w] switching frequency [khz] c load =4400pf c load =470pf c load =1000pf c load =2200pf at v dd = 15v pkg l j jl p t t max , max , max , ? = (35)
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 11 table 2. summary of high-side gate drive circuitry method basic circuit advantages & limitations high-side gate drivers for p-channel direct drive can be implemented if the maximum input voltage is less than the gate-to-source break down voltage of the device. open collector simple method, but is not suitable for driving mosfet directly in a high-speed application. level-shifted drive suitable for high-speed application and works seamlessly with regular pwm controller. high-side gate driv ers for n-channel direct drive easiest high-side application the mosfef and can be driven directly by the pwm controller or by a ground referenced driver, but it must meet two conditions, as follows: floating supply gate drive cost impact of isolated supply is significant. opto- coupler tends to be relatively expensive, limited in bandwidth, and noise sensitive. transformer coupled drive gives full gate control for an indefinite period of time, but is somewhat limited in switching performance. this can be improved with added complexity. charge pump drive the turn-on times tend to be long for switching applications. inefficiencies in the voltage multiplication circuit may require more than low stages of pumping. bootstrap drive simple and inexpensive with limitations; such as, the duty cycle and on-time are both constrained by the need to refresh the bootstrap capacitor. requires level shift, with the associated difficulties. q1 v cc l1 d1 pwm controller v cc r gate c out v out v out gnd out q1 gnd v cc l1 d1 pwm controller v cc v dc r gate c out v out v out out r pull q1 v cc l1 d1 pwm controller v cc v dc r base c out v out v out r 2 r gate r 1 gnd out q inv q1 v cc l1 d1 pwm controller v cc v dc r gate c out v out v out gnd out d scht miller gs cc dc max gs cc v v v and v v , , ? < < q1 v cc l1 pwm controller v cc v dc r gate c out v out v out q2 r gate gnd floating supply ho opto lo q1 v cc l1 pwm controller v cc v dc r gate c out v out v out q2 t1 r gate c block gnd out2 out1 q1 gnd v cc l1 d1 pwm controller v cc v dc c out v out v out out q1 v b in gnd ho v s v cc l1 in d1 hvic v cc v dc d boot c boot r gate c drv c out v out
AN-6076 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 12 consideration points of bootstrap circuit problem remedies of bootstrap circuit problem q1 v b in gnd ho v s v cc input d1 hvic v cc v dc d boot c boot r gate c drv c out the amplitude of the negative voltage is proportional parasitic inductances and the turn-off speed (di/dt) of the switching device, q1, which is determined by gate resistor, r gate , and input capacitance, c iss . l s1 l s2 latch-up, propagation signal missing and over- voltage across the bootstrap capactor if v s goes significantly below ground, the gate driver can have serious troubles. negative voltage transient at high-side switch turn-off. c c v dc +v gs,miller v dc v bs recovery time a-point b-point c-point v gs =b-c point i load i free a b gnd - v s v bs = (v cc -v fbd ) - (-v s )
AN-6076 application note disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reason ably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/30/08 13

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